Timing analysis of on-chip variation for GNSS chips based on the 22 nm process

Static timing analysis holds a crucial position in the realm of chip design. In the static timing analysis under the 22nm process, adopting the traditional on-chip variation (OCV) method will lead to problems such as inaccurate timing, unstable performance, and decreased design robustness. In order to improve the timing accuracy of the design and shorten its design cycle. An analysis method for a GNSS navigation chip based on 22 nm technology is proposed. The ICC2 tool is employed for layout and routing, while PrimeTime is used for static timing analysis. The design replaces fixed global parameters with local parameters following normal distribution, uses parametric on-chip variation (POCV) technology combined with path-based analysis (PBA) to model. Experimental results demonstrate that the method combines parametric on-chip deviation and path modeling. When compared to advanced on-chip deviation technology, it shows significant improvements: the worst negative slack (WNS) is optimized by approximately 56.2%, the total negative slack (TNS) is enhanced by around 82.2%, and the overall violation path count is reduced by 58.7%. This leads to substantial savings in timing analysis time, with an efficiency gain of up to 50.8%. This effectively demonstrates the strengths and weaknesses of the combined approach of POCV and PBA, leading to improved timing accuracy and shortened design cycle.