An 8T SRAM bitcell array-based compute-in-memory macro with high accuracy

To solve the bottleneck of power wall in traditional "von Neumann" architecture and improve the energy efficiency of multiplication and accumulation (MAC) in artificial intelligence applications, an in-memory computing circuit based on 8T static random memory array was designed to effectively avoid the "memory wall" problem. The bias voltage of the storage cell was designed to stabilize the charging and discharging currents, improve the linearity of the bitline discharge and increase the accuracy of the calculation. At the same time, the analog-to-digital converter (ADC) threshold coding was reduced and the area of the memory array was significantly reduced under the premise of ensuring the same discharge current. The circuit was designed based on a 65 nm CMOS process and accomplished a 64-Bite binary point multiplication and accumulation calculation function through a parallel calculation structure of 8\times72 memory arrays. Simulations show that a computational energy efficiency of 1.69 GOPS/W per bit is achieved in the 3-bit ADC output 8-bit comparison output mode, using core supply voltages of 0.8 and 1.2 V and a clock frequency of 250 MHz. Compared to the theoretical value baseline, the average calculation deviation of the calculated output is 1.05% maximum, effectively improving the calculation accuracy and reducing the circuit area.