A low on-resistance high-voltage SOI LDMOS structure using multiple P buried layers

In order to achieve low specific on-resistance (R_on,sp) and high breakdown voltage (V_BV), a low on-resistance high-voltage SOI LDMOS structure using multiple P-buried layers with step doping drift region was proposed and simulated. The PL-SOI LDMOS structure consists of several different P-buried layers with decreasing length and concentration in the vertical direction. Using multiple P-buried layers not only increases the doping concentration in the drift region, but also modulates the electric field in the drift region, resulting in R_on,sp reduction and V_BV enhancement. In addition to the SOI LDMOS structure with step doping drift region, the step doping distribution causes electric field peaks on the device surface, which can modulate the surface electric field distribution. The step doping drift region doping concentration rises from source to drain, can increase the breakdown voltage of the device, accommodate more impurity atoms and provide more electrons to support higher currents, thus reducing R_on,sp. PL-SOI LDMOS has a reduced R_on,sp(15.8 mΩ·cm² ) and an improved V_BV( 281 V). The structure was designed and simulated by Silvoca software to analyze the effect of structural parameters on device performance. In the case of the same drift region, the PL-SOI LDMOS has 35.8% lower R_on,sp and 55.2% higher V_BV than the conventional SOI LDMOS. The proposed structure has lower on-resistance and higher breakdown voltage, and the structure performance is improved.