Research on service reliability of 3D stacked packaging for ultrathin memory chip

With the increasing frequency and power of memory chips, 3D stacked packaging is difficult to meet the heat dissipation requirements of the chip, which is easy to cause chip warpage, cracking, and even interface delamination and other failure problems, seriously affecting the performance and service life of memory chips. To solve the above problems, the typical six layer stacked memory chip packaging structure is taken as the research object, and the chip junction temperature and maximum equivalent stress of the chip in service state are studied. Secondly, the combination of orthogonal test and grey correlation analysis is used to optimize the junction temperature and maximum stress of the chip, and the optimal combination of parameters is obtained. The simulation results show that the junction temperature of the optimized six layer stacked memory chip package structure decreases by 7.10%, and the maximum equivalent stress decreases by 9.67%. And it has certain guiding significance to the actual process development and industrialization.