Abstract: The promotion and application of the SM (Commercial Cryptography) algorithm is an important measure for strengthening information security in China. Increasing the speed of implementing encryption algorithms and reducing the hardware implementation costs have become urgent needs in practical applications. One solution to this problem is the FPGA hardware design and implementation of the SM4 algorithm based on composite fields. The solution reduces the number of hardware logic gates by using the composite field decomposition of the S-box and circuit optimization. In addition, the hardware circuit of the SM4 algorithm based on composite fields is restructured, and the generation and storage method of round constants and round keys are improved to reduce hardware area. Furthermore, a data communication mode is designed to enable communication between the host computer and the FPGA, providing secure support for the application through data encryption and decryption. The correctness of the SM4 algorithm based on composite fields implemented on FPGA hardware is verified through simulation testing and software and hardware implementation, and the throughput of the algorithm is improved. The comprehensive evaluation results show that the solution has a lower implementation area.