Abstract: Based on SMIC 0.18 μm 1.8V standard COMS process, a multifunctional pipeline ADC with a maximum of 12-bit 64 MS/s is designed. The ADC uses SHA_less, a 10-stage 1.5bit pipeline with 0.5bit redundancy, and a 2.5bit flash ADC architecture. Based on the different effects of the errors of each stage of the pipeline on the overall circuit performance, two kinds of variable gain operational amplifiers are designed to be used in the first three stages and the last seven stages of the pipeline respectively. The operational amplifiers used in the first three stages can achieve high gain and high bandwidth, and can also achieve low noise and reduce the equivalent input error of ADC. The bias current output buffer circuit is designed to provide different bias current for different op amp design of each stage. At the same time, the dynamic latch comparator without static power consumption is used to reduce the power consumption of the whole circuit. Multi-function module is added to make it can be used in a variety of occasions. At the input frequency of 9.39 MHz, the sampling accuracy of 12 bit and the sampling rate of 64 MS/s, the effective bit (ENOB) of 10.76 bit, the signal-to-noise ratio (SNR) of 66.5 dB and the spurious-free dynamic range (SFDR) of 81.4 dBc are achieved. The ADC has a power consumption of 50.2 mW and an area of less than 0.8 mm². This ADC can be integrated into the MCU as a built-in ADC, and is also suitable for baseband signal processing.