Abstract: To minimize the output jitter of the Bang-Bang digital phase-locked loop after lock-in, a new analytical modelling method for output jitter calculation is proposed. In this method, the digital-controlled oscillator (DCO) noise and limit-cycle noise are linearly superimposed. The filter coefficient of the phase-locked loop (PLL) is iteratively optimized based on the loop response speed, thereby improving the conditions for minimising output jitter. The proposed method provides theoretical support for the design of a high-performance digital phase-locked loop. According to the modelling method proposed in this paper, a Bang-Bang digital phase-locked loop is designed. The peak-to-peak jitter of the output clock is 5.56 ps@6 GHz, while the root mean square jitter is 1.33 ps@1 KHz~1 MHz, and the modelling error is less than 20%. Comparative results demonstrate that the system’s comprehensive modelling method has high accuracy and can be applied to the design of digital phase-locked loops with similar architectures.