Abstract: In order to solve the channel loss problem of four-pulse amplitude modulation serial signal in high-speed transmission, a half-rate decision feedback equalizer is proposed. The equalizer includes a continuous-time linear equalization unit, a limiting unit, a buffer, a half-rate decision feedback equalization unit, a decoder and a bandgap reference. The half-rate decision feedback equalization unit uses the odd-even dual-channel equalization technology to filter and compensate the signal at high frequency. The half-rate sampling clock effectively improves the signal equalization effect and reduces the power consumption of the equalizer. The equalizer is designed based on the 40 nm CMOS process, and the power supply voltage is 1.2 V. The simulation results show that under the environment of 40 Gbit/s data rate and 12.6 dB insertion channel loss, the additional peak-to-peak jitter of the two non-return signals decoded by the equalizer is 4.2 ps, and within 0.1 UI, the power efficiency is 1.98×10^－12 J/bit, which has high energy efficiency.