Abstract: With the evolution of IC process nodes, the continuous expansion of chip integration scale and the increase of operating frequency, the traditional clock tree synthesis strategy can't meet the timing requirements of current chip design. The clock concurrent optimization technology can't effectively solve the problem of routing congestion after clock tree synthesis and poor timing optimization of clock gated paths. To solve this problem, a clock tree optimization method combining early clock flow and CCOpt technology is proposed. The clock tree is constructed in advance in the placement stage, the clock tree routing, clock cell drivers and spacing are constrained, and the useful skew technology of CCOpt is used to optimize data and clock path at the same time to complete the clock tree synthesis. The proposed method is applied to the PCIe block in 6 nm process. The results show that the proposed method can effectively alleviate the routing congestion problem after clock tree synthesis. The worst negative slack is reduced by 63.6%, the clock gate path timing is optimized by 20.3%, the clock network power consumption is reduced by 1.54%, and the overall area is reduced by 1.8%. The performance of the chip is effectively improved.