Abstract: As the core component of the development of navigation products, the navigation GNSS chip has become more and more advanced with its process, and the power consumption problem has become a key factor affecting its development. At the same time, the traditional UPF (unified power format) low-power physical design process has shortcomings such as high error correction costs and difficult verification. This paper takes the DMAREQ_2 module of the GNSS chip under the TSMC 22 nm process as an example, and proposes V-UPF (Verfiery-UPF) process, which uses VC LP to verify the design files in a comprehensive static low power consumption before and after the physical design. In the design, multi-voltage domains are planned, a variety of special low-power units are inserted, and daisy chain connections and crossover layouts are used for power switch units to reduce system power consumption. Blockage technology is used to reduce the level signal conversion between voltage domains. Leakage and peak power dissipation. Finally, power consumption analysis is performed by Prime time-PX The results show that under different working environments, the total power consumption is reduced by up to 37.4%, the leakage power consumption is reduced by up to 45.2%, and the dynamic power consumption is reduced by up to 23.2%. The power consumption optimization effect of this design is remarkable.